For decades, Moore’s Law was an experimental rule defining the rate at which the customer demanded significant improvements in computing power and how fast manufacturers could furnish this request. Despite some bottlenecking in recent years, it has been a guiding inspiration for endless technological developments within manufacturing to best extract performance from shrinking transistor size but ballooning transistor count.
In many ways, high-speed PCB design has shadowed computational improvements in devices and innovations in new materials. Realizing the performance gains of high-speed designs requires additional planning and work to prevent unintended issues related to the greater energy inherent to higher speeds. Layout designers must know how best to achieve a board’s engineering goals and parameters without inhibiting functionality.
Comparing Low- and High-Speed PCB Design Practices |
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|---|---|---|
| Low-speed | High-speed | |
| Ground planes | The benefits of pouring copper anywhere outweigh most downsides. | Pour ground with caution, as it can lead to stray capacitance. |
| Guard rings | Prevent leakage current by maintaining consistent potential over the area. | Guard rings build capacitance at the inverting input of an amplifier. |
| Resistance values | Outside of its circuit function, the resistance value is manageable. | Large resistance values can form poles/zeroes in operational frequency from stray capacitance values. |
| Trace length | Short and direct routing is encouraged but optional. | Minimal trace lengths are a necessity to avoid trace inductance. |
The Physics of Signal Speed
Circuit behavior changes dramatically with an increase in frequency; minor issues relating to loss or distortion quickly compound and threaten to undermine signal integrity. High-speed design constraints factors include the following:
- EMI: High-speed return signals follow different transmission paths: instead of following the path of least resistance (the most direct possible path between points), return currents will follow the path of least impedance directly underneath the original signal. This pathing can result in significant radiation when passing over slots or splits in the reference plane due to the increase in the current loop. Be aware that tightly spaced via arrays can cut out large local portions of reference planes, contributing to circuitous return paths.
- Lossy substrate: Certain materials better contain electromagnetic fields’ energy than others. Designers should consult fabricators and manufacturers’ datasheets to determine what prepreg changes to make.
- Rise/fall times: Faster devices require a faster signal transition, which can cause issues during the associated switching periods.
- Crosstalk and coupling: The counterpart to radiated EMI, inductive coupling may result in signals that inadvertently conduct a signal, causing circuit behavior that can be difficult to diagnose. Extra care is necessary when routing and determining trace spacing in high-speed boards to eliminate the possibility of coupling. Greater spacing in an HDI board may require additional internal routing layers (when possible), and designers need to be mindful of routing signals too closely both in the layer and across adjacent layers; a cross-hatch pattern can be used for the latter coupling instances, e.g., routing vertically on layer three and horizontally on layer four.
Developing a Suitable Stackup
A proper high-speed design begins with material selection for low losses that meet the circuit’s required controlled impedances. To start, designers should determine their tightest pitch (i.e., the BGA, if present) to set the minimum trace width setting. Manufacturing to 3.5/4 mils is usually the extent of most fabricators’ precision, so make sure not to design around a value any smaller. From there, designers should grasp the routing density based on the net and component count.
The available board space will be a different story, and high-speed effects can negatively affect the density of the design. If ample space is available on the outer layers, the layout should take advantage and route as many traces as possible. More constrained boards may need additional routing on internal layers to achieve complete continuity. Reference plane placement will be critical: full-layer reference planes must be adjacent to a signal layer to prevent poor signal integrity. Ensure traces do not cross split-plane boundaries where there are adjacent power-plane layers.
Board thickness constraints may depend on the enclosure (especially if the board is part of a larger sub-assembly). This parameter will also affect the density by setting the minimum through-hole diameter. Through-hole vias can be a minimum of a tenth of the board thickness to prevent poor manufacturing outcomes during barrel plating, which may be an excessive reservation on HDI high-speed designs. To compensate, designers can opt for microvias that use sequential lamination drilling to enable a smaller drilled hole diameter; however, this is a considerable expense to standard fabrication with some process reliability concerns.
As traces lengthen, loss can become more noticeable and contribute to run-time errors while advancing the thermal aging of the board. Here, PTFE substrates are an excellent choice as their electrical characteristics exceed those of FR4. However, designers should be wary that manufacturing accommodations are necessary relative to the “standard” FR4, and thicker PTFE boards tend to suffer greater manufacturing defects. The fiber weave effect also merits discussion: the glass fibers that provide the structural integrity of most substrates have a different dielectric constant and loss tangent than the prepreg epoxy resin. Substrates with wider fibers and tighter weaves homogenize the background electrical characteristics and curb path dependency to minimize variance effects.
High-Speed Layout Strategies
Placement should focus on a centralized design where the components with the greatest fanout occupy the center of the board. Ideally, this minimizes the need for trace crossover while keeping the fanout traces short and direct for power efficiency. Like with a standard layout, route critical nets first – namely, clock, data lines, and differential pairs – and provide ample gaps for other fast-switching components.
At the extreme of high-speed designs mingling with slower frequencies, mixed-signal layouts will have to accommodate analog and digital components where the latter can significantly affect the performance of the former. Fast rise/fall times and the large associated slew rate (dV/dt) generate relatively strong electric fields that can couple to nearby traces and increase the noise. To prevent this interaction, designers must isolate analog signals apart from digital. While this technique should be readily apparent during layout, the return current through ground also requires consideration: designers will need to design an analog ground that is physically distinct from the broader digital ground – note that there is no potential difference (theoretically) between these “grounds,” as the definition of ground is a 0V reference. The analog and digital grounds will connect at a single location free of routing to confine the partitioned routes to their respective domain.
The final consideration will be methods to eliminate signal reflections. At any speed, reflections indicate an inefficient signal transmission, but signal transmissions can become damaging at high enough speeds due to the increasing energy. Fabricators can perform a post-plating depth-drilled step known as backdrilling to remove unnecessary stub length that can cause reflections.
Decoupling Capacitors: An MVP in High-Speed PCB Design
Capacitors fit many roles in a circuit, but none are as crucial to high-speed design as the decoupling capacitor. As its name implies, the decoupling capacitor’s primary function is to isolate a section of the circuit from other elements that could affect the former’s operational characteristics. This disturbance often comes in the form of noise or other transients flowing through the decoupling capacitor from a power net to ground instead of through the associated circuit element the capacitor is protecting. In this sense, decoupling capacitors act as a shunt, redirecting current through a low-impedance path.
Of course, impedance is frequency-dependent, and the performance of the decoupling capacitor also hinges on the changes in circuit behavior at various angular speeds. At DC and low frequencies, fully charged capacitors act like an open as they are unwilling to pass current once the negative plate fully saturates with electrons (the total amount depends on the strength of the dielectric). AC is another matter – because of the constant change in the direction of the current flow, capacitors can charge/discharge somewhat every cycle. In other words, instead of charge building up to a maximum like in DC, it is constantly being transferred between the two plates depending on the instantaneous direction of the current flow.
Calculating Bypass Capacitor Size |
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|---|---|
| Method #1 | Determine the capacitance according to the equation C = INtV, where I is the current necessary to switch from low to high, N is the number of outputs switching, t is the line-charge time, and V is the tolerable drop in VCC. t and V are assumed values. |
| Method #2 | Use the slew rate and the capacitance to calculate the current according to I = CdVdt. |
The decoupling capacitor, therefore, acts as a rudimentary highpass filter, allowing high frequencies (such as transients) to flow through to the ground. At the same time, DC is rejected and passed onto the associated circuitry. The difference in response is due to the capacitive reactance, an impedance component that approaches infinity at DC and zero at sufficiently high AC frequency. When decoupling capacitors operate in this manner, they are commonly called bypass capacitors.
Decoupling capacitors also helps ensure fast-switching components’ power is continuous and reliable. Acting as a reservoir for the primary power nets, capacitors placed near these elements prevent any issues related to many components drawing from the main nets to the point where the voltage dips noticeably below its rated value. Especially for analog devices, which are more likely to output any discrepancies in the power signal, this ultimately provides signal integrity by reinforcing the power busses of the board.
Your Contract Manufacturer Remains Up To Speed
High-speed PCB design encourages extra thought and brainstorming to navigate EMI and other issues. Successfully neutralizing these outgrowths of high speed while still capitalizing on the major benefits of these boards requires a development team that embraces the challenge at every point in the design. As a team of engineers committed to building electronics for our customers, we’re eager to meet the needs of today’s cutting-edge designs while preparing for tomorrow’s.
