Make no mistake: PCB design is initially a challenging design task. After all, whole industries are dedicated to software that supports designers in bringing a schematic to life based on input from engineers and manufacturers’ datasheets. Like any new task, it’s best to break up the lengthy and seemingly convoluted process into bite-sized pieces. This guide on PCB design tips and tricks looks over the entire design process from schematic to final documentation to discuss general guidelines for new designers to avoid common early pitfalls.
- Component Wizards: Part design should not be an overly lengthy process, with the possible exception of many unique parts and connectors. Entering a handful of standard dimensions for more standard SMT and TH packaging results in a land pattern that perfectly adheres to IPC standards. The incidents of errors are reduced, as is time spent during land pattern creation.
- 3D Models: Most major manufacturers will have 3D models of their parts available on their website or via contact form. The 3D models can give designers a good idea of dimensions above and below the board when appropriate (e.g., PCB enclosures) to avoid placing components anywhere they may otherwise conflict with their immediate surroundings. Further, 3D models can give a sense of potential solder shadows, whereby a significantly tall component prevents the flow of solder to those smaller components located too close behind the former, parallel to the direction of the wave.
- Verification: In a team setting where land patterns will be shared, the second pair of eyes can mean the difference between scrap/rework or components soldering down. While usually a recoverable setback in prototyping, this becomes a potentially expensive situation in larger production runs, costing an in-house production shop time and reputation.
- Part Substitutions: While pandemic responses are gradually subsiding, the supply chain is still unmitigatedly disrupted in the near future. Components in preferred packages may be unavailable, and second- or third-best options may need to be implemented. There isn’t much designers can do to circumvent this process, but luckily any changes to the BOM can be quickly rectified via netlist associations at the schematic level. Designers can even be proactive and create alternate part land patterns for components such that implementation only requires the aforementioned association and any minor routing cleanup.
While there are many variables in play, including the choice of substrate material, the trace factors that most directly influence the impedance will be the trace width and the dielectric height. The trace width is a bit of a misnomer, as the acid etching will form a trapezoidal shape due to the solution having more contact with the upper sides of the trace as it works around the etch protectant. The base of the trace is always wider than the top, and this measurement is generally provided as the “singular’ width of the trace (in reality, the top width will usually be about a half-mil shorter). From these two values and the inherent material properties, a vector field solver generates the impedance value. There’s an inherent advantage to thinner traces with routing — the thinner they are, the more can fit in the same area after considering spacing rules. Therefore, it is in a designer’s best interest to decrease the width while maintaining achievable production quality (usually no less than four mils), provided no other stack-up features trump this value.
Building the impedance profiles is only half of the stack-up usage. The designer will want to begin planning how they will distribute power planes, ground planes, and routing planes throughout the stackup to maximize signal and power layers while keeping reference plane distance to a minimum. Distribution should be balanced — think of the innermost core as a double-sided mirror. This method will not work for every design — sometimes, it may be necessary to borrow a plane layer for signal or vice versa, but it will often provide an excellent starting point. Ideally, routing planes should always have an adjacent ground plane on one side for reference. Most designers will insert ground planes on layers two and the second-to-last layer to reference the outer-layer signals, an internal power plane or signal layer on layers three, and the third-to-last layer. This stack-up monomer will continuously repeat on larger boards, though power or routing design needs may cause slight deviations.
1. Attention should be paid first to the most “central” signals or circuitry that represent the core functionality of the board and will have cascading effects if designed poorly. Usually, these will be things like data transfer lines, clock signals, and differential pairs. Prioritizing these project elements ensures there are no sacrifices involving their operation down the road.
2. Power circuitry design should include plenty of space around components and copper features to prevent induction in nearby traces, especially around switches. Whenever possible, follow the manufacturer’s guidelines on layout and routing guidelines; ample copper features for heat dissipation and reduced current density will prevent the creation of hotspots in the design that could lead to wear and failure. Capacitors will need to be arranged with capacitance increasing radially away from regulators/converters. Low capacitance nearby helps ensure that the quick charging/discharging elements are closest to the central power components while the less reactive capacitors are positioned further away. Ferrite beads are often used to reduce noise and clean up the input power signal before conversion. Keeping traces direct and short provides low impedance pathways for the circuit, which is especially crucial for a task as important as power generation/delivery.
3. If the board contains an FPGA, the pitch between pins/pads will likely be the most limiting factor in determining the spacing between traces and the via size. Some liberties may be taken concerning trace width within the routing channels between the FPGA pads. Unlike power circuitry, where it is generally preferred to have all circuitry on the same side of the board, FPGAs will often feature capacitors, resistors, and other associated devices underneath the relevant pins on the opposite side of the board. Partially, this is due to the much larger package size, as the in-plane distance between outer and inner pins can vary greatly. However, it is also important to realize that except for any components directly related to the clock, the requirement to shorten and provide direct routing from components to traces is not nearly as pressing for an FPGA as it would be for power circuits.
4. Routing should be direct and used via transitions no more than necessary. One method of organization is to have routing layers organized into alternating vertical and horizontal weaves. This serves two benefits: first, as an organization tool to maximize layer routing on dense boards. Secondly, alternating the travel direction minimizes plane-to-plane coupling on adjacent layers, which bolsters signal integrity and keeps actual impedance closer to targeted values.
5. The stackup and any sensitive equipment should be considered, especially regarding split power planes. Traces that reference multiple planes cannot be expected to possess their characteristic impedance described in the stackup due to poor return paths. This means that split or mixed planes constrain routing on the design layer where it’s being employed and any layers that reference said layer.
Feature Callouts: Uncommon board features that require attention, such as board cutouts, can be specifically called out in drawings to prevent being overlooked in the chain-of-design processes.
Silkscreen Legibility: Placing silkscreen text elements is difficult when SMD/TH component density reduces the spacing available for text. There are two approaches at this point. The first involves resizing silkscreen text to include as many components as possible. The tradeoff being text that is extremely difficult to read without magnification. While there is value in including as many identifier tags as possible, a greater legibility approach is including as many necessary/valuable silkscreen tags as possible without shrinking the text beyond some established minimum values. Generally, this would draw attention to test points first (useful for testers), IC components, and connectors. Resistors and components are generally of less concern than the aforementioned parts and would likely have their silkscreen text hidden away, where necessary. As an assurance, assembly drawings would still contain designators for all of the board’s components for ease of reference.
Document Readability: This follows somewhat from silkscreen legibility: viewing documents from the computer will be extremely different from reading them off a printed page. While it is trivial to zoom in on text in an online PDF with a rich dpi screen, reading small or unclear text is likely to lead to production issues, not to mention several calls and visits from the floor for clarification. Document elements like the drill chart should be quickly digestible with visually distinct legend symbols.
Fabrication/Assembly Notes: These notes will include general statements on standards and items relevant to the board’s specific processes during manufacturing. For customers, this provides an overview of previously agreed-upon processes that will provide the highest quality, yield, etc., of the final board. Tolerances will also establish guidelines for acceptability.