How to Reduce Parasitic Capacitance in PCB Layout

The term “parasitics,” as used by PCB designers, generally refers to any unwanted signal or power integrity effect in a PCB layout that can be modeled with a capacitor, inductor, or resistor. Parasitics are everywhere in an actual PCB layout, and they govern desired and undesired electrical behavior when it’s put into operation. For advanced circuit boards, like RF circuit boards and high-speed digital boards with large signal bandwidths, parasitic capacitance is the primary concern. 

While your PCB layout will never be completely rid of parasitics, you can reduce parasitic capacitance in a PCB layout or take some steps to limit its effects on signal and power integrity. Whether you’re engaging with a PCB service bureau or creating the layout yourself, follow some guidelines to ensure parasitic capacitance does not cause your design to fail.

What is Parasitic Capacitance?

Parasitic capacitance refers to an effect in a PCB layout where a propagating signal appears to behave as if it has interacted with a capacitor. This definition does not refer to a literal capacitor. Instead, signals propagating in certain regions of the PCB layout will behave as if a capacitor can divert the signal away from its intended channel, and the signal will see capacitive impedance along this alternative propagation path. High-frequency signal content can easily pass through this capacitor as a displacement current because the impedance will be lower than low-frequency signals.

Parasitics capacitance is responsible for several desired and undesired effects in a PCB layout, including:

• Bandlimiting behavior in transmission lines, producing low-pass filter behavior at very high frequencies
• Noise coupling between grounds at different potentials, leading to common-mode noise
• Noise or signal coupling into components, particularly in wire-wound inductors
• Capacitive crosstalk at high frequencies (appearing as FEXT and NEXT)
• PDN impedance modification due to spacing between power and ground planes
• EMI coupling into heatsinks, creating common-mode currents

The image below shows a simple example of how parasitic capacitance arises in a PCB layout. Within the PCB layout, we have an arrangement of conductors separated by an insulator, forming a complex structure with equivalent capacitance. This structure can be modeled as an arrangement of capacitors but note some parasitic inductance and resistance in this structure. It is this equivalent capacitance and inductance that determines impedances within a PCB layout.

General Tips to Reduce Parasitic Capacitance in a PCB Layout

The best way to think about parasitic capacitance is in regards to the structure of a capacitor. The geometry of conductors in the layout will need to change to modify parasitic capacitance.

Signal Integrity

The primary function of parasitic capacitance is to modify the path traveled by electromagnetic waves along an interconnect. This modification produces the following effects:

• Reduced impedance, typically due to proximity to grounded copper in the layout

• Higher return loss due to an impedance mismatch between an interconnect and a driver/receiver component

• Higher insertion loss due to the high-pass filtering behavior

The simple solution is to increase the spacing between the interconnect and any conductors that are not the desired reference plane. During design, the width of traces on a PCB should be carefully designed to account for any nearby conductors, especially nearby copper pour, to create a coplanar trace arrangement.

Copper pour issues are a common cause of the signal integrity problems listed above. An interconnect designer should take time to calculate the minimum clearance required between copper pour and their traces to ensure impedance control. Minimum clearance calculations can be performed with 2D or 3D field solver applications. An example calculation for Isola 370HR laminates with 50 Ohm CPW microstrips and striplines is shown in the graph below. After selecting the substrate height and determining the required trace width without copper pour, the curves below can help determine the minimum required clearance to prevent excessive impedance modification.

Power Integrity

Parasitic capacitance is both desirable and undesirable in power integrity. We can see this by comparing the structure of a PDN in a circuit board with a system involving multiple grounds. One common instance where parasitic capacitance is undesirable is found in systems with multiple ground points, such as a PCB power supply ground plane, a system ground region, and chassis ground. In these systems, and especially in high-current power supplies, parasitic capacitance can exist between the PCB ground planes and the chassis ground, allowing common-mode currents to travel through the system and radiate strongly.

Contrast this with a high-speed multilayer PCB. In these PCBs, the PDN should be arranged with at least one power/ground plane pair placed closely to provide high parasitic capacitance. This arrangement will help keep the PDN impedance at a low value over a broad bandwidth, which aids dampen power rail ripple when components on the board switch. The solution to high PDN impedance and imbalanced grounds are the same: use additional low ESL capacitors to provide decoupling and counteract noise.

At VSE, we understand the need to reduce parasitic capacitance in a PCB layout. We can help pinpoint potential SI/PI problems in your design before you send it into production. We also use the same types of sophisticated test methods used by high-volume CMs. If you’re designing advanced boards, like high-speed/high-frequency PCBs, take advantage of VSE’s design services and proprietary test methodology for evaluating board functionality.