As signal speeds continue to get faster and faster in circuit boards, designers must do more to ensure the best signal integrity in their layouts. One of those areas that require diligence in design is controlled impedance traces. High-speed transmission lines must have a carefully created trace structure to guide their path without differences in impedance that can distort the signal. Not only does this affect how the trace is routed, but also how the board layer structure is set up. Here is a brief look at impedance control in PCB design and how you can successfully set up your board for routing controlled impedance lines.
What Is Impedance Control in PCB Design?
Electrical impedance combines capacitance and inductance in the traces of a high-frequency circuit that creates opposition to the signal’s current flow. Although this opposition is measured in ohms the same way that resistance is, impedance is related to frequency, an AC characteristic. Resistance, on the other hand, is a DC characteristic. Impedance can vary in value at different points along the length of the trace, which can degrade the signal’s quality. This risk of degradation makes impedance control in high-frequency circuits essential for signal integrity.
The circuit board’s traces behave differently at higher frequencies than regular connections and will act more like high-speed transmission lines instead. If one of these lines has different values of impedance scattered throughout it, the miss-matches could create reflections of the original signal traveling back in the opposite direction. The magnitude of these reflections will depend on the differences between the impedance values. If large enough, they could distort the signal and interrupt the intended function of the circuit.
It is essential to control the signal’s impedance values during trace routing to ensure the best signal integrity and the continued high-frequency performance of the circuit board. However, many factors affect the impedance of a trace, including the circuit board’s materials and the trace parameters. We’ll look further into these details next.
Impedance Control Layout Considerations
Impedance-controlled routing begins with the schematic. Design engineers should specify their controlled impedance signals’ values and types so that the layout team understands which nets are single-ended or differential pairs. This specification can be done using the design tool’s rules and constraints to set up different net classes for controlled impedance routing or notating it on the schematic.
To ensure that the same impedance values are maintained throughout the length of a controlled trace, the following parameters must be considered for routing:
- Trace geometry: The width and thickness (copper weight) of the trace being routed.
- Signal spacing: The spacing between the signal trace and its return path is usually on the adjacent reference plane layer. This will be controlled with the configuration of the board layer stackup.
- Dielectric material: The core and prepreg materials used on either side of the controlled impedance trace layer. Their thickness and dielectric constant will be part of the impedance calculations.
PCB layout designers need to calculate these parameters with the circuit’s impedance requirements to determine the appropriate trace width for routing. To perform these calculations, designers can usually use the trace impedance calculators built into their design tools. There are also circuit simulators that will provide these calculations and different online calculators and charts.
When it comes time to start routing your controlled impedance traces in the layout, here are some considerations to keep in mind:
- Trace widths: Make sure that the controlled impedance traces are distinguished from other nets to help the PCB manufacturer easily spot them. During manufacturing, these trace widths will often need subtle changes, which can be complicated if the traces aren’t highlighted. They can be highlighted by setting up net classes in the design data or specifying a slightly different trace width value in the Gerber files.
- Differential pairs: These traces have to be routed parallel to each other with consistent spacing between them. Do not split the pair around obstacles like vias, and arrange their via fanouts to keep lines symmetrical.
- Spacing to other objects: Controlled impedance lines need to be isolated from other routings, and a good rule of thumb is to use three times the trace width for their clearances. If your controlled impedance line is five mils, you should allow 15 mils clearance to other traces and components. Using your design rules and constraints to set up net classes for controlled impedance lines will help you set and maintain the extra spacing you need.
- Clear signal return paths: Ensure that the reference planes adjacent to your controlled impedance routing will provide you with a clear return path. A blocked return path is one of the most common sources for EMI problems in a circuit board.
How to Work Together with Your CM on Impedance Controlled Designs
With the number of high-speed designs in use today, PCB contract manufacturers are finding most of their work in controlled impedance routing circuit boards. They are positioned to help you with the material and configuration choices you need to make for your project due to their experience. Here is some of the information that they will need from you to get started:
- Net names of controlled impedance signals
- Target impedance for single-ended and differential pairs
- Routing layers of the circuit board for the controlled impedance traces
- Desired raw board materials
At VSE, we will use your design data and manufacturing drawings, as well as our DFM tools and experience, to validate your design against the requested board materials. If we find any discrepancies, we will work with you to bring the target impedance values within their specified range. While other PCB CMs can’t help their customers like this, our standard process is to use as much of your information as possible to give you the highest level of quality.