PCB layout can be challenging, but high-speed constraints and demands can transform challenging into demanding. Increasing signal speeds means standard design best practices must account for insignificant material characteristics at slower speeds. While some high-speed PCB design guidelines overlap with traditional layout methodology, designers must understand the differences and how they affect their layout strategy.
| Navigating the Challenges of High-Speed PCB Design Guidelines | |
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What is a High-Speed PCB?
High-speed PCB design can be a bit nebulous: there is no strict delineating point where a design transitions from “regular” to high-speed. There are three design aspects to consider:
- The highest frequency in the circuit’s highest-speed signals.
- The fastest rise/fall time for digital circuitry.
- The maximum data transfer rate.
Note it’s not necessary to evaluate a circuit on all three characteristics; just one high-speed qualifier is sufficient. However, edge cases exist: designers should usually weigh a 1 GHz-and-up board as high speed, but this is not always valid. Designs with higher speeds than the arbitrary 1 GHz cutoff don’t always require high-speed accommodations, while some boards with slower speeds do. Ultimately, board speeds around and above 1 GHz should indicate a high-speed design, but designers will want to tread carefully to avoid overconstraining designs and imperiling yield and profitability.
A more involved method of high-speed criteria is analyzing the length of the longest interconnection against the wavelength. When interconnection lengths are at least 1/12th as long as the shortest wavelength in the design, it’s reasonable to consider the design high-speed. This qualifier can be slightly confusing, as it weighs the entire length of the interconnection, e.g., the trace length and any cable length for off-board connections. It behooves designers to communicate with system engineers to determine the actual length of interconnections once installed to avoid underestimating the high-speed needs of the board.
When in doubt, prototype builds are the stage where designers can iterate board layouts with relatively low financial stakes. Best practices dictate designers should keep trace lengths as short as possible to reduce impedance during signal transmission, which dovetails with high-speed guidelines. Other high-speed PCB considerations include:
- Transmission lines – While it was possible to treat traces as simple interconnections in the past at lower speeds, high-speed design dictates that every interconnection meeting high-speed criteria must observe best practices to curtail distortion, crosstalk, and electromagnetic interference (EMI). Due to the increased bit rates, fidelity becomes an issue even with short distances spanned in high-speed designs.
- Power integrity – For all designs, the stability of power and ground reference planes is crucial to maintaining stable performance. However, high-speed designs complicate the situation with the greater proliferation of high-frequency noise. Maintain proper filtering and layout to avoid noise coupling to the reference planes.
- Stackup – The components, design intent, and other factors shape the conductive and insulative materials comprising the board stackup. Additionally, material considerations become more pronounced in high-speed designs: as signal frequency increases, the relative dielectric constant decreases. Because of the varying dielectric constant, the different frequency components of the waveform then arrive at the load asynchronously and produce distortion. This distortion also increases with faster speeds.
High-Speed PCB Design Guidelines for Layout
Treating interconnections as transmission lines requires controlling for impedance – keeping the impedance constant during transmission reduces distortion effects. Provided the transmission line maintains its characteristic impedance from source to load, resonance is impossible as there are no impedance discontinuities. Primarily, transmission lines differ from more general interconnections by weighing the directional trace and return paths (i.e., the current loop). When constructing the stackup, designers use EM field-solver software that calculates the characteristic impedance using the dielectric thickness, trace width, and trace gap (for differential pairs). Differential pairs are handy for controlled impedance structures; since designers define the return path on the same layer adjacent to the signal trace, both traces experience identical electrical characteristics (assuming best practices).
To optimize the layout, designers should follow these effective methods for optimal signal integrity:
- Differential pairs – Route differential pairs adjacent to each other with consistent spacing as defined in the stackup/design rules. Address length-matching discrepancies at the point(s) of divergence. Return vias are necessary for every differential pair layer transition; ensure these vias are equidistant from their respective trace via. Avoid placing components or vias in the gap between the differential pair traces, as the gap can produce impedance discontinuities. In-line component placement is acceptable so long as the component placement is symmetrical.
- Length-matching – With controlled impedance and identical dielectric background, the only remaining factor affecting signal propagation is the length of the trace. While differential pairs are the typical example of length-matching, data lines requiring synchronous processing are another candidate. Route all traces of the same group of signals on the same layer – via transitions or differences in trace dimensions between layers can introduce delays. Within the group of signals, determine the “shortest-longest” trace – that is, the shortest distance between the furthest driver and receiver – then add the appropriate length to the remaining traces.
- Reference planes/split-planes – Controlled impedance structures that don’t use a planar return path (i.e., standard differential pairs and coplanar waveguides) use the nearest reference plane for their return path (the path of least impedance). This return path poses issues when the reference plane is inconsistent for the length of the current loop. Designers should avoid routing over split planes or plane gaps at all costs, as these return paths are prodigious EMI sources. If routing over split planes or plane gaps is unavoidable within the context of the design, a stitching capacitor across the planes adjacent to the trace can reduce the EMI by passing high frequencies and shrinking the current loop.
Your Contract Manufacturer Accelerates High-Speed PCB Turnaround
Due to the increasing demands of digital circuits, high-speed PCB design guidelines are essential for modern board performance. For designers or design teams who need help ensuring their high-speed board is production-ready, VSE is here to help. Our engineers are committed to building electronics for our customers, including a full design review for manufacturability and optimal performance. VSE has been realizing life-changing and life-saving devices with our valued manufacturing partners for over forty years.
