PCB Trace Width and Spacing: Optimizing HDI Layouts

Printed circuit board designers must communicate the manufacturing intentions of a project so that there aren’t any problems in building the board. To do that, consider all ways to ensure that data in PCB design documentation is as straightforward as possible.

In the layout, designers must balance the circuit’s optimal needs against the board’s constraints (size, thickness, materials, etc.). While designers have significant freedom to route the board, best practices dictate the methods to reduce signal crosstalk and improve performance (excluding more specific instructions in the manufacturers’ datasheet.) Primarily, crosstalk is a function of the proximity between traces i.e., PCB trace width and spacing; however, several design factors can intensify or alleviate this and other electromagnetic interference (EMI) issues.

Optimizing PCB Trace Width and Spacing
	Intra-plane coupling	Inter-plane coupling
Width	3.5 mils is the lower bound for manufacturability for many applications without significantly impacting yield. While most signal traces are unaffected by a width reduction, use wider traces on power/ground nets and other signals as recommended in manufacturers’ datasheets.	While trace widths on adjacent signal layers are more likely to be closer to the minimum width manufacturability (i.e., there is rarely power/ground signal routing internally outside of designated layers), be mindful of differences in trace widths for broadside coupling
Spacing	The three-width (3W) rule optimizes air gap based on trace width. On outer layers, avoid routing close to fast-switching components (think inductors in switched-mode power supplies)that can generate significant magnetic fields.	To minimize broadside coupling, use the 5H rule: the horizontal distance between layer-adjacent signal planes should be five times the distance apart from the vertical distance from the trace to the nearest reference plane. Use cross-hatch routing on adjacent signal planes to minimize parallelity between traces.

How Coupling Affects PCB Trace Width and Spacing

The circuit board routing process has become more complex in recent decades as package circuit density and pinouts have increased exponentially. To correctly manage the signal integrity of the many traces required to connect a board’s nets, PCB designers must be cognizant of how signals can indirectly influence each other:

• Capacitive coupling – A capacitor functions as an electric field reservoir by creating a potential difference between two parallel plates separated by a dielectric. Capacitive coupling occurs unintentionally when the layout of the board’s elements – like the parallel edges of two closely routed traces – replicates the basic structure of the capacitor and adds a parallel capacitance to the circuit, as seen by the signal. Capacitive coupling increases with greater parallel plate area, shorter distance between plates, and the material’s dielectric strength between the plates.
• Inductive coupling – Unlike capacitive coupling, which reproduces the structure of the capacitor, inductive coupling has nothing to do with the inductor as a discrete circuit element. Ampère’s Law states that the current flow produces a magnetic field centered about the conductor (with the field’s curling direction determined by the current flow’s direction). Inductive coupling increases as the current increases, the rise/fall time of the signal increases (digital lines have a reputation for adding significant noise to analog lines for this reason), the distance of and between parallel trace segments, and the impedance of the two traces.

A common rule of thumb for many PCB manufacturers is to adopt the 3W (three-width, also sometimes referred to as the three-height or 3H rule) that establishes a relationship between the current-carrying capacity of the trace and the distance to the nearest trace. As the trace widens in any dimension, its impedance drops correspondingly, which can support higher currents. However, the higher currents create stronger magnetic fields, so designers use a three-width spacing (measured from the center line of the trace) to scale a larger air gap between traces with a wider trace. Since the air gap is proportional to the width of the traces, wider traces (think power, GND, and other high-current nets) will have the minimum spacing to prevent interference, and narrower traces will allow for denser routing.

Differences in Routing Within and Between Signal Planes

While it’s easy to conflate coupling concerns with intra-signal plane routing, inter-signal plane routing can also be an avenue for EMI. Especially for signal planes in a stackup without reference plane separation between them, coupling between traces on adjacent planes can become significant. Here, instead of the height and length of the trace forming the coupling planes, the width and length are the capacitor plates. This difference intensifies EMI issues since the trace width is usually much larger than the trace height.

There’s also the factor of parallel trace lengths on adjacent planes: when routing in the plane, even traces with considerable parallel runs will have some separation to prevent a short. However, traces on adjacent planes can occupy the exact relative plane position throughout their entire run after accounting for vias. The broadside coupling effect becomes more challenging to minimize by increasing the air gap between traces, which would unnecessarily increase the thickness of the stackup, increasing production costs and potentially rendering the entire design unsuitable for applications that require a thin board profile. Moreover, crosstalk reduction is less effective when the air gap between parallel inter-plane traces increases compared to parallel intra-plane traces.

Addressing Broadside Coupling

The solution is to increase the separation of the traces by shifting them horizontally relative to each other, moving them out of a parallel alignment. Why is this more effective than a greater air gap when the traces remain parallel? Transferring magnetic energy and storing an electric field within a capacitor requires parallelity. An increase in an offset angle (up to total perpendicularity) reduces their effectiveness. In this scheme, where the vertical distance from a trace to the nearest reference plane is some height  “H,” the horizontal spacing between adjacent inter-plane traces should be a minimum of 5H. Alternatively, designers can use a cross-hatch method on alternating signal layers to minimize the length and occurrence of parallel trace sections.

Your Contract Manufacturer Prioritizes Signal Integrity

PCB trace width and spacing are the primary factors undermining signal integrity and amplifying crosstalk. Detriments range from inconsistent or ambiguous real-time performance to permanent damage to components (including the board). Furthermore, these optimal widths and airgaps are not a simple one-size-fits-all: depending on the board’s design intent, different materials and the manufacturers’ precision act as notable constraints. If you’re looking for an experienced PCBA manufacturer, look no further: at VSE, our engineers are committed to building electronics for our customers. We’ve been realizing life-saving and life-changing products for over forty years with our manufacturing partners.