The term “parasitics,” as used by PCB designers, generally refers to any unwanted signal or power integrity effect in a PCB layout, usually modeled with a network of ideal impedance devices (resistor, capacitor, inductor). Parasitics are everywhere in an actual PCB layout and govern desired and undesired electrical behavior during operation. Parasitic capacitance is the primary concern for advanced circuit boards, like RF and high-speed digital with large signal bandwidths.
While your PCB layout will never be completely absent of parasitics, you can reduce parasitic capacitance in a PCB layout or take some steps to limit its effects on signal and power integrity. Whether engaging with a PCB service bureau or creating the layout, follow these guidelines to ensure parasitic capacitance does not cause your design failure.
What is Parasitic Capacitance?
Parasitic capacitance refers to an effect in a PCB layout where a propagating signal behaves as if it has interacted with a capacitor. This definition does not refer to a literal capacitor: signals propagating in some areas of the PCB layout will behave as if a capacitor can divert the signal away from its intended channel, and the signal will see a capacitive impedance along this alternative propagation path. High-frequency signal content can easily pass through this capacitor as a displacement current because the impedance will be lower than low-frequency signals.
Parasitic capacitance is responsible for several desired and undesired effects in a PCB layout, including:
- Bandlimiting behavior in transmission lines, producing low-pass filter behavior at very high frequencies
- Noise coupling between grounds at different potentials, leading to common-mode noise
- Noise or signal coupling into components, particularly in wire-wound inductors
- Capacitive crosstalk at high frequencies (appearing as FEXT and NEXT)
- PDN impedance modification due to spacing between power and ground planes
- EMI coupling into heatsinks, creating common-mode currents
The image below shows a simple example of parasitic capacitance in a PCB layout. Within the PCB layout, we have an arrangement of conductors separated by an insulator, forming a complex structure with equivalent capacitance. This structure is primarily an arrangement of capacitors but also includes some parasitic inductance and resistance. This equivalent capacitance and inductance determines impedances within a PCB layout.
Example of parasitic capacitance between two microstrip traces and between the two traces and the nearby ground plane.
Methods to Reduce Parasitic Capacitance
| Mutual capacitance | Designers can simplify mutual paired inductance using the same technique as a Wheatstone bridge, i.e., the diagonal capacitance product must be the same as the branch capacitance product. |
| Mutual inductance | A Y-Δ transform can change a T-filter with the capacitor as the parallel element to a 𝜋-filter with capacitors as the parallel elements and an inductor in series. This method is applicable for direct/inverse coupling and one-sided capacitance networks. |
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General Tips to Reduce Parasitics in a PCB Layout
The best way to think about parasitic capacitance is regarding the structure of a capacitor. The geometry of conductors in the layout will need to change to modify parasitic capacitance.
Signal Integrity
The primary function of parasitic capacitance is to alter the path traveled by electromagnetic waves along an interconnect. This modification produces the following effects:
- Reduced impedance, typically due to proximity to grounded copper in the layout
- Higher return loss due to an impedance mismatch between an interconnect and a driver/receiver component
- Higher insertion loss due to the high-pass filtering behavior
The simple solution is to increase the spacing between the interconnect and any conductors that are not the desired reference plane. During design, the width of traces on a PCB must account for any nearby conductors, especially nearby copper pour, to create a coplanar trace arrangement.
Copper pour issues commonly cause the signal integrity problems listed above. An interconnect designer should take time to calculate the minimum clearance required between copper pour and their traces to ensure impedance control. Minimum clearance calculations resolve with 2D or 3D field solver applications. The graph below shows an example calculation for Isola 370HR laminates with 50 Ohm CPW microstrips and striplines. After selecting the substrate height and determining the required trace width without copper pour, the curves below can help determine the minimum required clearance to prevent excessive impedance modification.
A coplanar waveguide comparison for microstrip and striplines shows the differences in parasitic capacitance.
Power Integrity
Parasitic capacitance is both desirable and undesirable in power integrity, depending on the requirements of the network at that particular point; this becomes apparent by comparing the structure of a PDN in a circuit board with a system involving multiple grounds. One typical instance where parasitic capacitance is undesirable is for systems with multiple ground points, such as a PCB power supply ground plane, a system ground region, and a chassis ground. In these systems (and especially in high-current power supplies), parasitic capacitance can exist between the PCB ground planes and the chassis ground, allowing common-mode currents to travel through the system and radiate strongly.
Parasitic capacitance to a device chassis will create a path for common-mode current when the PCB ground plane and the chassis ground are at slightly different potentials.
Contrast this with a high-speed multilayer PCB. The PDN in these PCBs requires at least one power/ground plane pair spaced closely to provide high parasitic capacitance. This arrangement will help keep the PDN impedance low over a broad bandwidth, dampening power rail ripple when components on the board switch. The solution to high PDN impedance and imbalanced grounds is the same: use additional low ESL capacitors to provide decoupling and counteract noise.
At VSE, we understand the need to reduce parasitic capacitance in a PCB layout. We can help pinpoint potential SI/PI problems in your design before you send it into production. We also use the same sophisticated test methods used by high-volume CMs. If you’re designing advanced boards, like high-speed/high-frequency PCBs, use VSE’s design services and proprietary test methodology for evaluating board functionality.
