Idealized models of common physics and engineering topics are the perfect learning tools because they introduce complex subjects without real-world nuances. Capacitors are perfect in introductory electromagnetism and network analysis courses: there are no losses associated with energy transformation that would further complicate equations. Much like a frictionless surface, this is impossible to achieve in a real-world setting. The reverse is also true: wherever there’s a dielectric between two planar surfaces, some capacitance (known as stray capacitance) causes expected circuit behavior to deviate. Designers and manufacturers have to account for stray capacitance by limiting its occurrence and counteracting its effects where present during prototype testing.
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What Causes Stray Capacitance?
The possibility for stray capacitance is ubiquitous throughout a circuit board. Within the plane, closely spaced parallel traces form a capacitor, as do conductor surfaces between vertical layers in the stackup (this stray capacitance is an essential factor in calculating controlled impedance structures). Cables also form capacitance between adjacent wires’ parallel surfaces and between the wires and shielding sheath. Calculating the capacitance of these capacitors is trivial:
where C is capacitance, εr is the relative permittivity of the material, ε0 is the free space permittivity, A is the area of the plates, and d is the normal distance between the plates. Therefore, capacitor strength grows with higher relative permittivity, larger parallel plate surface areas, and shorter distance between the plates (and vice versa). Note that layer-to-layer stray capacitance dominates over stray capacitance from trace height due to the larger surface area.
It’s critical to understand that unlike parasitic capacitance (which is always considered a contributing factor to nonideal circuit behavior), stray capacitance is unavoidable as it’s a function of the board’s construction. Stray capacitance is not necessarily a nuisance; as mentioned, characteristic impedance transmission lines require a stray capacitance to calculate the impedance. It can become an issue with signal lines not meant for external interfacing, e.g., high-speed signals slow down, and amplifier circuits can experience ringing and oscillations that undermine signal integrity or potentially damage board components.
Identifying and Correcting Stray Capacitance During Layout
Additional layout strategies can also invite unintentional stray capacitance into the design:
- Ground pours – Flooding ground on external signal layers is common for low-speed circuits (sub-1 MHz), as the pour functions as bypass capacitors throughout the layout and decreases overall inductance. However, this technique can significantly contribute to stray capacitance at high speeds.
- Guard rings – Similar to ground pours, guard rings provide excellent isolation and prevent current leakage at low signal speeds, but high speeds create stray capacitance at the input. Capacitance can cause performance to suffer or produce runtime errors at the inverting input.
- Large resistors – The combination of large impedance (above several kilohms) and low stray capacitance can form a pole or zero within the operating range of high-speed frequencies.
Designers wishing to limit the stray capacitance during design for non-characteristic impedance transmission lines can use a few layout techniques to minimize its presence:
- Bypass capacitors – Current only flows in a closed loop. This simple statement is one of the fundamentals of any circuit analysis, but it also belies a secondary point: electrical current wants to flow in a closed loop and will attempt to return to its source. Bypass capacitors provide a pathway to the ground that limits the loop area of this return current.
- Reduce trace width – Reducing the width of the trace decreases the layer-to-layer surface area available and thus the capacitance. Reduce the width with care, as an overly thin trace will not only be challenging (and costly) to fabricate but may also suffer increased inductance.
- Reduce trace length– Similar to the trace width, reducing the length reduces the surface area and capacitance, but there’s little downside to shortening the trace length. Wherever possible, shorten trace lengths.
- Increasing normal distance between planes– Physically spacing signal layers and reference layers decreases the capacitance. However, this solution may be unavailable in high-layer count boards or those with tight thickness constraints due to enclosure/system integration.
- Removing reference plane beneath signal– There’s no capacitor without a reference layer below the signal layer. Removing reference layers under signal layers should be done with extreme caution! Routing over split planes or gaps in planes becomes a significant source of electromagnetic interference (EMI).
Note that reference layers include ground and power planes since power planes function as AC ground.
Your Contract Manufacturer Optimizes Designs Pre-Production
Stray capacitance is unavoidable in electronic design, but designers can mitigate its effects by carefully analyzing the layout and stackup. While this capacitance most noticeably affects high-speed signal performance, designers can still see benefits at lower speeds, especially for amplifier networks. Whatever your design calls for, VSE can help optimize your layout pre-production. We’re a team of engineers committed to building electronics for our customers, including a thorough design analysis to identify potential manufacturing issues at the earliest stage of board development. We’ve been realizing life-saving and life-changing devices for over forty years with our valued manufacturing partners.
If you are looking for a CM that prides itself on its care and attention to detail to ensure that each PCB assembly is built to the highest standards, look no further than VSE. Contact us today to learn more about partnering with us for your next project.
