PCB Etch Factor: Balancing Trace Width and HDI

I spent much of my early childhood digging holes – whether snow, dirt, or sand, I couldn’t get enough of seeing how far I could dig down before I met some impenetrable subsurface and lost interest. One of the frustrations I discovered was how much time I had to spend digging the sides of the hole rather than straight down. Standing inside an excavated hole was fun, but the interesting part was seeing how far down I could get (also, Mom was less likely to notice the deep holes than the wide ones).

PCB manufacturers face a similar challenge: when removing copper during etching, signal integrity would improve greatly if they could only etch straight down. With traditional etching processes, this is impossible, and etching occurs both in the plane and along the sides of the newly exposed copper. The PCB etch factor relates the vertical and horizontal etching rate and considerably affects impedance values and EMC.

The PCB Etch Factor’s Impact on DFM

	Design	Manufacturing
Trace Width	Sets one of the lower limits of design density The smallest trace width necessary to accommodate the tightest pitch breakout (typically BGA)	Etching shapes the trace from an ideal rectangular cross-section into a filet Reducing the top base of the fillet creates an error relative to the target impedance
Crosstalk	Most designs follow the 3W rule for trace spacing, i.e., a minimum of 3 trace widths between traces measured center-to-center	Smaller trace widths closer together cause more inductance due to an increase in proximity and a decrease in surface area

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The Impact of PCB Etch Factor on PCB DFM

A PCB’s etch factor results from the board fabrication process that produces the copper features. To rapidly process boards with dense, intricate copper designs, manufacturers use an applied layer of etch resist that protects the desired copper while introducing an etchant bath to remove the unprotected copper. Consider the copper surface at the time of application: the copper layer is uniform in thickness and free from defects at the macro level, meaning the etchant can only attack copper from the surface (excluding the copper treated with etch resist). As time goes on, however, the etchant wears away the surface – this does not affect the unprotected copper; however, the copper underneath the protective etch resist layer becomes exposed to the etchant solution. While the surface of the unprotected copper is consistently flat, the copper underneath the etch resist is a 3D structure where the etchant can attack the sides.

Specifically, the etch factor is definable based on some exposed and unexposed copper lengths underneath the copper resist. Imagine a trapezoid forming as the top base shrinks (due to side access by the etchant, which will have more contact with the side copper closer to the surface) while the bottom base is undisturbed – it matches the width of the applied etch resist. The etch factor is a mean of differences between the top and bottom bases divided by the height of the trapezoid. The value between zero and one (often reported as a percentage) indicates the etch factor, with a small etch factor equating to little undercut (difference between etch resist width and the copper width of the top base of the trapezoid). Truthfully, the trapezoid shape is a slight simplification: the side-attack of the copper by the etchant produces fillets not unlike solder joints, but the trapezoid is less rigorous to calculate without sacrificing much accuracy.

The width of the copper at the top of the trapezoid is an important measurement, reported as the trace thickness, and used alongside the height and bottom base to calculate impedance values. Manufacturing difficulty will also use the trace width thickness as a barometer (among other constraints) for yield and cost calculations. Most fabricators will bottom out at approximately 3.5 mil/~90 micron trace width thickness (as always, the best course is to speak to a manufacturer to assess technology sophistication) due to reliability issues; designers need to understand that etching copper is a well-controlled process, and excessive undercutting can not only hamper the physical integrity of the trace but also disrupt targeted impedances. Understandably, designers will want to minimize trace width before adopting other methods of increasing interconnect density (layer addition and via size reduction) as it incurs no additional processing costs.

Manufacturing Limits on Trace Width, Shape

Another element to consider with a PCB etch factor is the rate of increasing inaccuracy in trace-width shape as the size decreases. A common method of qualifying trace etch quality is an equivalent trapezoid angle – a 30°-45°-60° classification corresponding to under-etched, nominally-etched, and over-etched, respectively. When trace widths are relatively large at ~6 mils / 200 microns, the difference in impedance between each subsequent etching level should be ~1 Ω for a 50 Ω trace (in other words, 2% error). However, at ~1.5 mils / 50 microns, this error doubles to approximately 4%. Considering the importance of impedance matching for power delivery and signal integrity, the HDI gains (producibility aside) are rarely worth the loss in performance when other methods are available only for a cost increase.

One thought might be to bypass the etch factor entirely and focus on producing rectangular cross-section traces; indeed, this trace shape shows little deviation between targeted impedance and measured impedance, even at width dimensions far below what’s ordinarily manufacturable. While this level of precision is possible with current-day manufacturing technology, it is exceptionally cost-prohibitive for most prototypes and unfeasible for any mass production.  Signal crosstalk is another issue: even if manufacturing can eventually push down trace widths without sacrificing quality, signals residing closer to each other with less surface area will experience an increase in inductance due to both contributors. This increasing inductance makes it easier for nearby traces to couple and EMI to become more pronounced throughout the design.

Your CM Factors Into Production Success

The PCB etch factor may be a simple calculation, but it carries wide-reaching implications for the board’s performance following fabrication. Designers need to consult with manufacturing to avoid common DFM pitfalls that exceed machine and process capabilities; other methods of improving board density, like shrinking via sizes or adding additional layers, may be an option instead. Prompt communication of all design constraints can expedite manufacturing by improving yield and preventing unnecessary revisions. At VSE, we’re a team of engineers committed to building electronics that exhibit exceptional reliability and quality for our customers. For over forty years, alongside our manufacturing partners, we’ve continued to realize life-saving and life-changing devices.