In chemical reactions that favor a total conversion of products to reactants, reactions proceed until one or more are consumed, based upon stoichiometric ratios. These reactants, known as limiting reagents, represent the upper limit of efficiency.
Much the same for PCBs, the manufacturability of a board is heavily constrained by the smallest producible features. By determining minimum trace widths, spacing, and via hole/pad sizes for the component with the tightest pitch (typically the BGA), designers and manufacturers set guidelines for design that have various knock-on effects. The number of routing channels created between these design rules and the package shapes the density of the routing layers.
Multilayer PCB stackup planning will combine this information with the total number of signals, power, and return paths and design a layer configuration that promotes excellent signal integrity. Deciding upon a final stackup will consider both the board’s requirements and cost/manufacturability concerns.
How To Decide Upon a Layer Count
Before deciding on the arrangement of layers in the stackup, designers must determine the total layers at their disposal. This process could include input from the engineering team and manufacturers. However, sometimes the designer will be tasked with defining this board element. On the design end: the fewer the number of layers, the tighter the manufacturing tolerances. And broadly speaking, signal integrity suffers due to coupling, routing too close to noise sources, etc. Along the same lines, setting trace widths to one mil and designing via structures with aspect ratios > 10:1 will result in a board that is unproducible or extremely cost-inefficient with current manufacturing technology, likely necessitating a complete revision.
The economic value of reducing layers is great, especially for designs intended for mass production. With careful placement and layout, designers can wring all the usable board space without sacrificing performance. Additional layers also contribute to overall thickness, which will have downstream effects on elements of the board and its box build, such as the vibrational sensitivity, the total size of the enclosure, thermal requirements for cooling, and more. Generally, designers can be more liberal on layer count with prototypes and small production runs. However, it still represents added cost to the customer, and the possibility of extensive revisions at a later point may preclude a smooth transition to production.
How can a designer decide upon an acceptable layer count that doesn’t hamstring them, the manufacturer, or incur unnecessary costs to the customer? Certainly, practice and experience play a large role, but there are more immediate methods designers have at their disposal:
- First, set the design rules according to the most demanding component. For a BGA, this may look like four mil trace width/clearance and 8/20 mil via hole and pad. Note that these values are towards the higher end of manufacturing shop capabilities and, therefore, more expensive. If able, designers can relax these constraints to reduce costs in larger production lots, provided the decided-upon design rules can still complete the design.
- To run a quick check on the feasibility of the layer count, run the autorouter. An autorouter should be nearly able to complete routing on its own if the layer count is adequate. Care should be taken that unless stipulated in settings or design rules, the autorouter will make some performance liberties. The goal of the autorouter in this setting is not to offer guidance but to evaluate the routing density — doubling as a valuable assessment of component placement.
Multilayer PCB Stackup Planning: From Impedance to Layer Allocation
Once a layer count is decided upon, designers can further customize the stackup. The two major decisions will be the material construction of the layers and the distribution of signal and plane layers to balance routing density against power delivery and short return paths. Specialty software containing impedance field solvers will accurately determine manufacturing variables before entering into production. Designers must be cognizant of the impedance needs throughout the design. Typically, single-ended traces will be 50 ohms, and differential pairs will be set to 100 ohms, though the latter has many exceptions. Impedance structures need only be defined upon the layers they’re used. For example, 90-ohm USB-affiliated differential pairs that only run along an outer layer do not require an equivalent impedance structure on an inner layer.
Equally important to both material selection and stackup design will be the concept of board symmetry. For fabrication and assembly processes, the behavior of a symmetric board about the core is significantly easier to predict. Especially for heat-intensive processes, such as lamination and solder wave/reflow, a balanced design is far less likely to encounter thermomechanical failures like via barrel cracking or warpage due to the material coefficient of thermal expansion mismatches.
Choosing materials will depend on both availability at the fabrication shop (or direct from the manufacturer’s supply) and any special requirements of the board. High-speed designs may require low dissipation factor materials to support signal integrity and inhibit excess heat generation. Another concern may be the tightness of the weave, which can increase propagation delay on signals due to dielectric fluctuations between the weave-rich and weave-poor substrate areas. For length-matched signals, this unintended delay can pose timing issues.
The designer will need to assign layers as signals and planes at this point. While this will affect the impedance calculations due to the amount of copper removed during the etching process, the designer’s issue is how the arrangement will impact the ease of routing, signal integrity, and board performance. Stackups are open to a vast amount of variance depending on the particular needs of a design. A great starting point is looking at the board through the lens of ground distribution. Signal and power layers should neighbor a reference plane for short and direct return paths. Provided are some sample stackups for various layer counts; notice that new ground or signal/power layers are added alternating towards the center as layer count increases, pushing previous layers outward. This generalized form can be expanded to a board of any number of layers.
| 4 | 6 | 8 | 10 |
| Unused | Unused | Unused | Top |
| Top | GND | ||
| Top | GND | SIG | |
| Top | GND | SIG | PWR |
| GND | PWR/SIG | PWR | GND |
| PWR | PWR | PWR | GND |
| Bottom | GND | SIG | PWR |
| Unused | Bottom | GND | SIG |
| Unused | Bottom | GND | |
| Unused | Bottom |
See How Your Contract Manufacturer Stacks Up
Multilayer PCB stackup planning must be approached from a multitude of design and manufacturing angles. Cost, production viability, and performance quality compete on any board. Still, an experienced designer can analyze and plot a course best suited to meet the original design intent. If your board is facing issues related to the stackup that have resulted in extensive revisions or rework during production, we can help. At VSE, we’re a team of engineers committed to designing electronics for our customers. Together with our professional manufacturing partners, we’ll deliver a board that meets all specifications while exceeding expectations.
