When designing a board for production, the issue of copper thickness comes into play as early as the impedance calculations of the stackup software. While its contributions to the overall board thickness are a performance factor, the resulting processing constraints that shape layout design rules are far more critical. Designers will want to speak to a manufacturer at the earliest possible point pre-layout to optimize the board’s manufacturing.
Conversion Chart for Copper Thickness
| Copper weight (oz./sq. ft.) | Thickness (mils/µm) | Recommended minimum air gap/trace width (mils/mm) |
| 1 | 1.37/34.8 | 3.5/0.089 |
| 1.5 | 2.06/52.2 | Consult with a manufacturer. |
| 2 | 2.74/69.6 | 8/0.203 |
| 3 | 4.11/104.4 | 10/0.254 |
| 4 | 5.48/139.2 | 14/0.355 |
| 5 | 6.89/174 | Consult with a manufacturer. |
| 6 | 8.22/208.8 | |
| 7 | 9.59/243.6 | |
| 8 | 10.96/278.4 | |
| 9 | 12.33/313.2 |
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Cutting Through Copper Thickness Idiosyncracies
Designers encountering copper thickness values for the first time may need clarification: listed values are in weight, not length. The convention here is pressing the given weight of the copper flat across a one sq. ft. area, which correlates to the thickness, for example, a conversion of 1 oz. to 1.37 mils / 34.8 microns. While initially unintuitive, the system is quickly navigable and gives designers a quick estimate of the copper contributions to the overall board thickness alongside additional weight for projects where reducing the latter may be a mission-critical objective. The copper thickness as a weight is also helpful for current-carrying calculations where the circuit demands require additional material.
The copper thickness of a layer can be quite context-sensitive. To a vendor, the copper thickness would only indicate the installed thickness pre-processing. This value won’t change for an inner layer of a nonsequential lamination, but it would change for an outer layer, i.e., the manufacturer’s reported thickness. The discrepancy is due to the plating process for vias to establish vertical continuity that adds additional thickness from electrodeposition; manufacturers must ensure that the thickness values used in impedance calculations match those of the final, post-plated thickness. In other words, stackup copper thicknesses should represent finished thicknesses, and the manufacturer has the leeway to achieve this most cost-effectively while meeting all design specifications.
Different Thicknesses For Different Applications
Like the distribution of layers about the center of the board, the copper in the top and bottom halves should be equal to prevent processing issues. The issue lies with etching: exposure to an etching solution removes uncovered copper on the laminate as a time-dependent function. The etchant would continue to eat away at the copper until total removal from the substrate or saturation of the solution, meaning there’s no feasible method to chemically etch simultaneously at different rates on the top and bottom during submersion.
However, the thickness of copper layers doesn’t otherwise have to be uniform – it’s common in high-power applications to use thicker copper on the outer layers to withstand the greater currents (and temperatures) from the associated components. On the other hand, copper thickness above the minimum is hugely detrimental to HDI boards due to the need for many discrete traces for dense component net breakout. As the copper thickness grows, so does the minimum gap between copper features due to the etching process: the etchant solution must remove all vertical copper from the base substrate to prevent shorts. However, because the etch resist patterns can only protect the copper directly underneath, the etch solution begins to attack the newly revealed copper from the sides, forming the trapezoidal traces designers are familiar with. The longer time available for a side-attack of the traces by the etch solution means the in-plane distance between traces naturally increases.
Manufacturers will also scale the artwork for etch compensation to address the lateral etch of copper features underneath the etch resist application. This compensation factor will increase copper features while decreasing the air gap between them. In this sense, the scaling counteracts the increased air gap for thicker coppers (although scaling occurs for all thicknesses, not just those > 1 oz.) The relationship between the minimum gap and thickness is linear; intuitively, power circuitry typically needs larger area pours than several individual traces routed across the board, so there’s little sacrifice necessary when reducing routability for these board types.
The Impact of Thickness on Impedance
Copper thickness will also affect the impedance calculations of the stackup layer structures. Focusing on surface microstrips, an increase in the trace width decreases the impedance for the former according to the equation provided by IPC-2141
where εr is the relative dielectric constant, h is the height, t is the thickness, and w is the width of the microstrip. This equation is relatively straightforward, but it lacks accuracy, especially for exceedingly thin traces; one alternative is the equation provided by Brian C. Wadell in Transmission Line Design Handbook:
with terms
where η0 is the impedance of free space and w’ is the equivalent zero-width thickness track given by a final equation of
There’s a lot of math to digest here: the critical takeaway (besides trace impedance calculations should be left to the computers) is that trace density and trace width (and therefore, impedance) are in varying degrees of opposition, with greater copper thicknesses further restricting the lower limit of trace widths between nearby traces according to the minimum air gap form during etching. While the math becomes more complex to determine the impedance of nearby traces due to coupling effects, the general point holds: designers will want to consider trace width constraints when designing impedance structures in the stackup.
Your Contract Manufacturer Through Thick and Thin
Selecting between laminates for assembly stackups based on copper thickness can be challenging if designers lack familiarity with fabrication. To optimize the stackup and board performance, manufacturers will select among available stock (on-site or through vendors) that meets design specifications while accounting for process limitations. At VSE, we’re a team of engineers committed to building electronics for our customers that outperform expectations. We’ve built life-changing and life-saving electronics with our valued manufacturing partners for over 40 years.
